Semiconductor wafer and manufacturing method thereof

ABSTRACT

A semiconductor wafer manufacturing method comprising the steps of preparing first and second semiconductor wafers, bonding a main surface of said second semiconductor wafer to a main surface of said first semiconductor wafer, thinning said first semiconductor wafer, implanting oxygen ions from said first semiconductor wafer side into a neighborhood of a part where said first and second semiconductor wafers are bonded to each other, and forming the portion implanted with the oxygen ions into an oxide film layer by a thermal treatment.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser.No. 11/223,970, filed Sep. 13, 2005, which is a divisional applicationof U.S. application Ser. No. 10/461,352, filed Jun. 16, 2003, and claimspriority to Japanese Patent Application 2002-285160 filed Sep. 30, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor wafer and amanufacturing method thereof.

2. Description of the Background Art

In a conventional SOI (Silicon On Insulator or Semiconductor OnInsulator) wafer, an oxide film layer resides on one main surface of asupporting substrate wafer made of, e.g. a silicon substrate, and an SOIlayer resides on the top surface of the oxide film layer. Such SOI andoxide film layers are formed by bonding to the supporting substratewafer an SOI layer wafer that has a silicon substrate with an oxide filmformed on its main surface and then removing part of it.

After the supporting substrate wafer and the SOI layer wafer are bondedtogether, an unwanted portion of the SOI layer wafer is removed byadopting a method such as SMART CUT® or ELTRAN®; refer to PatentDocument 1 shown below.

When a MOS (Metal Oxide Semiconductor) transistor is formed in the SOIlayer, it is arranged so that its channel direction is parallel to a<100> crystal direction of the SOI layer, for example. It is known thatarranging the channel direction in parallel with <100> crystal directionenhances the current driving capability of the P-channel MOS transistorby about 15 percent and also reduces the short-channel effect.

It is thought that the current driving capability is enhanced becausethe hole mobility in <100> crystal direction is larger than that in<110> crystal direction, and that the short-channel effect is reducedbecause the value of the boron diffusion coefficient in <100> crystaldirection is smaller than that in <110> crystal direction.

Now, with SOI wafers, the SOI layer wafer, in which SOI and oxide filmlayers are formed, may be bonded to the supporting substrate wafer withtheir crystal directions shifted at 450 (or 135°) with respect to eachother. Specifically, the two wafers are bonded together in such a waythat a <100> crystal direction of the SOI layer and a <110> crystaldirection of the supporting substrate wafer coincide with each other.The reason is shown below.

(100) wafers cleave along {110} crystal planes. Accordingly, when theSOI layer wafer and the supporting substrate wafer are bonded togetherso that the <100> crystal direction of the former coincides with the<110> crystal direction of the latter, the wafer can be cleaved, forexperiments and studies, along {110} cleavage planes of the supportingsubstrate wafer 1 that forms a large part of the wafer thickness. On theother hand, in the SOI layer whose crystal direction is shifted, an MOStransistor can be formed so that its channel direction is parallel witha <100> crystal direction.

Thus, when cleaved, the supporting substrate wafer 1 breaks along <110>crystal direction, while the SOI layer breaks along <100> crystaldirection. In this way, bonding the two wafers with their crystaldirections shifted from each other provides the advantage that a sectionalong the MOS transistor channel direction can be easily exposed.

The following list shows prior art reference information related to thepresent invention:

Patent Document 1: Japanese Patent Application Laid-Open No.2002-134374,

Patent Document 2: Japanese Patent Application Laid-Open No. 9-153603(1997), and

Non-Patent Publication 1: G. Scott et al., “NMOS Drive Current ReductionCaused by Transistor Layout and Trench Isolation Induced Stress,” (US),IEDM, 1999.

A conventional SOI wafer is manufactured by a method shown below, forexample.

First, an SOI layer wafer and a supporting substrate wafer are prepared,both of which are a (100) wafer having a (100) plane as a main surface.Next, a notch (or an orientation flat) is formed at a <100> crystaldirection edge of the SOI layer wafer and a notch (or an orientationflat) is formed at a <110> crystal direction edge of the supportingsubstrate wafer. Then, the two substrates are bonded together in such away that the <100> crystal direction of the SOI layer and the <110>crystal direction of the supporting substrate wafer coincide with eachother.

In this bonding process, the two wafers are bonded so that the notch ofthe supporting substrate wafer and the notch of the SOI layer wafercoincide with each other. However, when the two wafers are positioned byutilizing these notches only, the SOI layer <100> crystal direction andthe supporting substrate wafer <110> crystal direction may not beprecisely aligned.

With such a positioning error between wafers, the MOS transistor channeldirection cannot be precisely aligned with the SOI layer <100> crystaldirection and a deviation is caused between the two. This is because MOStransistors are formed on the basis of the position of the supportingsubstrate wafer.

Then the current driving capability of the MOS transistors cannot beenhanced satisfactorily. Furthermore, electric characteristic variationswill occur among MOS transistors formed on the surfaces of different SOIwafers.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide asemiconductor wafer and a manufacturing method thereof in which thecurrent driving capability of a MOS transistor can be sufficientlyenhanced.

According to a first aspect of the present invention, a semiconductorwafer includes a first semiconductor wafer and a second semiconductorwafer.

The first semiconductor wafer has a plurality of cuts formed at edgeportions in crystal directions, and the second semiconductor wafer has acut formed at an edge portion in a crystal direction.

One of the plurality of cuts of the first semiconductor wafer and thecut of the second semiconductor wafer are formed in different crystaldirections. The first and second semiconductor wafers are bonded to eachother with said one of the plurality of cuts of the first semiconductorwafer and the cut of the second semiconductor wafer coinciding with eachother.

The first semiconductor wafer has a plurality of cuts and the first andsecond semiconductor wafers are bonded together in such a way that oneof the plurality of cuts of the first semiconductor wafer and the cut ofthe second semiconductor wafer coincide with each other. That one of theplurality of cuts of the first semiconductor wafer and the cut of thesecond semiconductor wafer are positioned in different crystaldirections. Thus, when the two wafers are bonded together using thecoinciding cuts for positioning, another cut of the first semiconductorwafer can be engaged with a guide portion of the semiconductor wafermanufacturing apparatus to prevent positioning error due to relativeturn between the wafers. This allows the two wafers to be highlyprecisely positioned. Thus the semiconductor wafer can be easily cleavedso that a section along MOS transistor channel direction is exposed, anda MOS transistor having a remarkably enhanced current driving capabilitycan be formed on the semiconductor wafer.

According to a second aspect of the present invention, a semiconductorwafer manufacturing method includes the following steps (a) to (d). Inthe step (a), first and second semiconductor wafers are prepared. In thestep (b), a main surface of the second semiconductor wafer is bonded toa main surface of the first semiconductor wafer. In the step (c), oxygenions are implanted from the first semiconductor wafer side into aneighborhood of a part where the first and second semiconductor waferare bonded to each other. In the step (d), the portion implanted withthe oxygen ions is formed into an oxide film layer by a thermaltreatment.

After the first and second semiconductor wafers are bonded together,oxygen ions are implanted and the oxygen-ion-implanted portion isprocessed into an oxide film layer through a thermal treatment. Thus, bybonding together the first and second semiconductor wafers in crystaldirections shifted from each other, it is possible to form an SOI waferthat includes an SOI layer and a supporting substrate having crystaldirections shifted with respect to each other. Furthermore, forming theoxide film layer by oxygen ion implantation and thermal process providesan SOI wafer with reduced SOI layer thickness nonuniformity. The reducedSOI layer thickness nonuniformity enhances the current drivingcapability. Thus the semiconductor wafer can be easily cleaved so that asection along the MOS transistor channel direction is exposed, and anMOS transistor having a remarkably enhanced current driving capabilitycan be formed on the semiconductor wafer.

According to a third aspect of the present invention, a semiconductorwafer manufacturing method includes the steps (a) to (e). In the step(a), a first semiconductor wafer having a plurality of cuts formed atedge portions in crystal directions is prepared. In the step (b), asecond semiconductor wafer having a cut formed at an edge portion in acrystal direction that is different from the crystal direction of one ofthe plurality of cuts of the first semiconductor wafer is prepared. Inthe step (c), the first and second semiconductor wafers are bonded toeach other while using said one of the plurality of cuts of the firstsemiconductor wafer and the cut of the second semiconductor wafer inorder to position the first and second semiconductor wafers, withanother one of the plurality of cuts of the first semiconductor waferbeing engaged with a guide portion of a semiconductor wafermanufacturing apparatus. In the step (d), oxygen ions are implanted fromthe first semiconductor wafer side into a neighborhood of a part wherethe first and second semiconductor wafers are bonded to each other. Inthe step (e), the portion implanted with the oxygen ions is formed intoan oxide film layer by a thermal treatment.

After the first and second semiconductor wafers are bonded together,oxygen ions are implanted and the oxygen-ion-implanted portion isprocessed into an oxide film layer through a thermal treatment.Accordingly, by bonding together the first and second semiconductorwafers in crystal directions shifted from each other, it is possible toform an SOI wafer that includes an SOI layer and a supporting substratehaving crystal directions shifted with respect to each other.Furthermore, forming the oxide film layer by oxygen ion implantation andthermal process provides an SOI wafer with reduced SOI layer thicknessnonuniformity. The reduced SOI layer thickness nonuniformity enhancesthe current driving capability. Thus the semiconductor wafer can beeasily cleaved so that a section along MOS transistor channel directionis exposed, and a MOS transistor having a remarkably enhanced currentdriving capability can be formed on the semiconductor wafer. Moreover,in the step (c), the first and second semiconductor wafers are bondedtogether with another one of the plurality of cuts of the firstsemiconductor wafer engaged with a guide portion of the semiconductorwafer manufacturing apparatus. This prevents positioning error due torelative turn between the wafers. Thus the two wafers can be highlyprecisely positioned and a MOS transistor with a sufficiently enhancedcurrent driving capability can be formed on the semiconductor wafer withthe two wafers bonded in different crystal directions with respect toeach other. Furthermore, electric characteristic variations are lesslikely to occur among MOS transistors formed on different semiconductorwafers.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is the top view of a semiconductor wafer according to a firstpreferred embodiment;

FIG. 2 is a cross-sectional view of the semiconductor wafer of the firstpreferred embodiment;

FIGS. 3 to 5 are cross-sectional views showing a bonding process forforming the semiconductor wafer of the first preferred embodiment;

FIG. 6 is the top view of a semiconductor wafer manufacturing apparatusthat is used in the semiconductor wafer bonding process of the firstpreferred embodiment;

FIG. 7 is a cross-sectional view of the semiconductor wafermanufacturing apparatus used in the semiconductor wafer bonding processof the first preferred embodiment;

FIG. 8 is a diagram depicting the semiconductor wafer bonding process ofthe first preferred embodiment; and

FIGS. 9 to 11 are cross-sectional views showing a semiconductor wafermanufacturing method according to a second preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Preferred Embodiment

FIG. 1 is the top view of a semiconductor wafer according to thispreferred embodiment. This semiconductor wafer 100 is a (100) wafer thathas a (100) plane as its main surface (in FIG. 1, the circle containinga point inside represents an arrow that shows the normal direction tothe (100) plane. FIG. 2 shows the II-II section of FIG. 1.

The SOI wafer 100 includes a supporting substrate wafer 1 formed of,e.g. a silicon substrate, an oxide film layer 2 resides on one mainsurface of the supporting substrate wafer 1, and an SOI layer 32 resideson top of the oxide film layer 2. This SOI layer 32 and the oxide filmlayer 2 are formed by bonding to the supporting substrate wafer 1 an SOIlayer wafer that has a silicon substrate and an oxide film formed on itsmain surface and then removing part of it. While the SOI layer 32 andoxide film layer 2 and the supporting substrate wafer 1 generally haveapproximately the same diameter, their diameters may be somewhatdifferent from each other depending on the manufacturing process.

Semiconductor devices, including MOS transistors and interconnectionsamong them, are formed in the surface of the SOI layer 32. The MOStransistor TR1 of FIG. 1 is an example of such a semiconductor device.In the MOS transistor TR1, “S” denotes its source, “D” denotes itsdrain, and “G” denotes its gate.

This MOS transistor TR1 is arranged so that its channel direction isparallel with a <100> crystal direction of the S01 layer 32.

In the semiconductor wafer 100, the supporting substrate wafer 1 has anotch 1 a formed at an edge portion in a <110> crystal direction and theSOI layer 32 has a <100> crystal direction notch 32 a and a <110>crystal direction notch 32 b.

The bonding of the supporting substrate wafer and the SOI layer wafer isnow described, where a SMART CUT method is shown by way of example.

Before bonding, the oxide film layer 2 is formed on a surface of an SOIlayer wafer 320 and a crystal defect layer DF is formed by a hydrogenion implantation IP2 in a portion deeper than the oxide film layer 2 bythe thickness DP1 of the SOI layer 32 (see FIG. 3).

Next, as shown in FIG. 4, the oxide film layer 2 of the SOI layer wafer320 is bonded to a main surface of the supporting substrate wafer 1. InFIG. 4, the position of the bonded plane is shown as BD. Note that thesupporting substrate wafer 1 and the SOI layer wafer 320 are bonded sothat their <100> crystal directions are at an angle of 45° or 135° withrespect to each other.

Next, a thermal treatment is applied to weaken the crystal defect layerDF and the SOI layer wafer 320 is separated at the crystal defect layerDF as shown in FIG. 5. At this time, the peripheral portions of the SOIlayer wafer 320, which are not bonded firmly, are also removed. FIG. 5shows the dividing plane as DT.

Then the structure is further heat-treated to increase the bondingstrength between the SOI layer 32 and the supporting substrate wafer 1,and the surface of the SOI layer 32 is lightly polished to remove theresidue of the crystal defect layer. The semiconductor wafer 100 shownin FIGS. 1 and 2 are obtained in this way.

Next, the process of bonding the supporting substrate wafer 1 and theSOI layer wafer 320 is described in greater detail. The bonding processis performed by using a semiconductor wafer manufacturing apparatus asshown in FIGS. 6 and 7, for example. FIG. 7 shows the VII-VII section ofFIG. 6.

This manufacturing apparatus includes a holder HD for holding thesupporting substrate wafer 1, a wafer guide GD2 used as a guide forpositioning the SOI layer wafer 320 to be bonded, and an air pin AP forsucking and holding the semiconductor wafer. FIG. 6 shows the SOI layerwafer 320 with broken line and clearly depicts the supporting substratewafer 1 underneath.

The holder HD has a recess HL having a depth DP2, where the supportingsubstrate wafer 1 is placed. A raised portion HLa is formed at the edgeof the recess HL; the supporting substrate wafer 1 is placed there withthe raised portion HLa engaged with or fitted in the notch 1 a.

The wafer guide GD2 is a guiding member that is situated on the holderHD to surround the recess HL. The raised portion HLa is extended also onthe wafer guide GD2 so that it can be engaged also with the notch 32 aof the SOI layer wafer 320.

The wafer guide GD2 includes another raised portion GD1 that can bemoved back and forth along the arrow Q shown in the drawings. The raisedportion GD1 can be moved to protrude from the wafer guide GD2 toward theSOI layer wafer 320, so that it can be engaged with the <110> directionnotch 32 b of the SOI layer wafer 320. The raised portion GD1 and theraised portion HLa are positioned on the wafer guide GD2 at an angle of45° with respect to each other. The raised portion GD1 is situated at alevel higher than the supporting substrate wafer 1 placed in the recessHL so that it will not touch the supporting substrate wafer 1 when it ismoved.

When this manufacturing apparatus is used, the raised portion GD1 is setin the withdrawn position in the wafer guide GD2, the supportingsubstrate wafer 1 is placed in the recess HL of the holder HD, and thenthe raised portion GD1 is moved to protrude from the wafer guide GD2.Next the SOI layer wafer 320 is carried with the air pin AP and moveddown onto the supporting substrate wafer 1 so that the notch 32 a andthe notch 32 b are engaged respectively with the raised portions HLa andGD1, and then the SOI layer wafer 320 and the supporting substrate wafer1 are bonded together. Subsequently, the raised portion GD1 is withdrawninto the wafer guide GD2 and the bonded wafers 1 and 320 are pulled upand taken out with the air pin AP.

When the depth DP2 of the recess HL is sized smaller than the thicknessof the supporting substrate wafer 1, the supporting substrate wafer 1placed in the recess HL slightly protrudes above the surface of theholder HD. In this case, when the raised portion GD1 is moved toprotrude from the wafer guide GD2, the bottom of the raised portion GD1and the surface of the supporting substrate wafer 1 are not excessivelyspaced apart, and then the SOI layer wafer 320 can be put down whileensuring the engagement between the notch 32 b and the raised portionGD1.

During this process of bonding the two wafers, they are positioned sothat the notch 1 a of the supporting substrate wafer 1 and the notch 32a of the SOI layer wafer 320 coincide with each other, while the notch32 b of the SOI layer wafer 320 is engaged with the raised portion GD1that serves as a guide member of the semiconductor wafer manufacturingapparatus.

Note that “the notch 1 a and the notch 32 a coincide with each other”does not mean that their shapes perfectly coincide with each other. Forexample, the depths of the two notches 1 a and 32 a in the wafer radiusdirection may somewhat differ from each other. Also, the central anglesof the two notches 1 a and 32 a, i.e. the angle between the two sides ofeach “fan” shape, may somewhat differ from each other. The notch 1 a andnotch 32 a work as long as their shapes coincide with each other to suchan extent that the positioning can be achieved precisely.

Thus, the raised portion GD1 engaged with the notch 32 b limits theturning movement of the SOI layer wafer 320 in the wafer planedirection, which makes it possible to more effectively preventpositioning error due to relative turn between the wafers, than inconventional bonding process where wafers are positioned using only thenotches 1 a and 32 a. Thus the wafers can be highly preciselypositioned, so that an MOS transistor TR1 having a sufficiently enhancedcurrent driving capability can be formed on the semiconductor wafer,with the two wafers positioned in crystal directions shifted from eachother. Furthermore, electric characteristic variations are less likelyto occur among MOS transistors TR1 formed on different semiconductorwafers.

Note that the rest of the semiconductor wafer 100 manufacturing process,other than the bonding process, may be conducted by adopting othermethod, such as an ELTRAN method, as well as the SMART CUT method.

This preferred embodiment thus provides a semiconductor wafer and amanufacturing method thereof in which the <100> crystal direction notch32 a and the <110> crystal direction notch 32 b are formed in the SOIlayer wafer 320 and the two wafers 1 and 320 are bonded together withthe <100> crystal direction notch 32 a and the <110> crystal directionnotch 1 a of the supporting substrate wafer 1 coinciding with each other(see FIG. 8).

As shown above, the SOI layer wafer 320 has the notches 32 a and 32 b.Accordingly, while the supporting substrate wafer 1 and the SOI layerwafer 320 are positioned by utilizing the notch 1 a of the wafer 1 andthe notch 32 a of the wafer 320, the notch 32 b of the SOI layer wafer320 can be engaged with a guide member of the semiconductor wafermanufacturing apparatus to prevent positioning error between the wafersthat would be caused if the wafers turn relative to each other. Thisallows the two wafers 1 and 320 to be precisely positioned. As a result,it is easy to cleave the semiconductor wafer to expose a section alongthe MOS transistor channel direction, and it is possible to form an MOStransistor with a sufficiently enhanced current driving capability onthe semiconductor wafer.

While this preferred embodiment has shown an example in which the SOIlayer wafer 320 and the supporting substrate wafer 1 are bonded togetherto form an SOI wafer, the present invention is not limited by thisexample. That is to say, the present invention can be applied also tobulk wafers that have no oxide film layer 2. That is, the presentinvention can be applied to the formation of a bulk wafer in which twobulk wafers are bonded together with their crystal directions shiftedfrom each other, so as to form a bulk wafer whose surface crystaldirection differs from that in the deeper portion.

Also, while this preferred embodiment has shown an example in whichnotches are used to indicate crystal directions, any cuts of othershapes, such as orientation flats, may be used to show the crystaldirections.

Moreover, while this preferred embodiment has shown an example in whichthe notches 32 a and 32 b are formed in the SOI layer wafer 320respectively in <100> and <110> crystal directions, the invention is notlimited by this example. Notches 32 a and 32 b may be formed indirections other than <100> and <110> crystal directions, and they maybe positioned in other relationship with respect to each other.

Second Preferred Embodiment

This preferred embodiment shows a method suited to manufacture SOIwafers in which, as shown with the semiconductor wafer 100 of FIG. 1, anSOI layer and a supporting substrate wafer are bonded in crystaldirections shifted from each other.

FIGS. 9 to 11 are cross-sectional views showing a semiconductor wafermanufacturing method according to this preferred embodiment.

First, an SOI layer wafer 321 and a supporting substrate wafer 1, bothof which are a semiconductor wafer that has a (100) plane as a mainsurface, are prepared and bonded together in such a way that a <100>crystal direction of the SOI layer wafer 321 and a <110> crystaldirection of the supporting substrate wafer 1 coincide with each other(see FIG. 9). FIG. 9 shows the position of the bonded plane as BD. Atthis stage, no oxide film layer exists on the SOI layer wafer 321 andthe supporting substrate wafer 1.

Preferably, in this bonding process, a plurality of notches are formedon the edge of the SOI layer wafer 321 as has been shown in the firstpreferred embodiment and the two wafers are precisely positioned byusing the semiconductor wafer manufacturing apparatus shown in FIGS. 6and 7. However, this preferred embodiment is not limited to thisexample.

Next, the surface of the SOI layer wafer 321 is processed by grinding,CMP (Chemical Mechanical Polishing), chemical treatment or the like, soas to thin the SOI layer wafer 321 to form a semiconductor layer 322(see FIG. 10). The thickness TH of the semiconductor layer 322 may beabout 100 to 1000 nm, for example.

Next, an oxygen ion implantation IP1 is applied from the semiconductorlayer 322 side into the portion where the two wafers are bonded to eachother (into a neighborhood of the bonded plane BD). Then the structureis thermally processed at a temperature of about 1300° C. to 1400° C. toform the oxygen-ion-implanted portion into an oxide film layer 2. Thusthe portion of the semiconductor layer 322 that is left unoxidized formsthe SOI layer 32 (see FIG. 11). The dosage of oxygen ions can be 1×10¹⁷to 1×10¹⁸ cm⁻², for example.

According to this preferred embodiment, the SOI layer wafer 321 and thesupporting substrate wafer 1 are bonded together with their crystaldirections shifted from each other, implanted with oxygen ions, andthermally processed to form the oxygen-ion-implanted portion into theoxide film layer 2.

In general bonding methods, an oxide film layer is formed on a surfaceof one wafer and then this wafer is bonded to another wafer, without theneed for oxygen ion implantation. However, nonuniformity of the filmthickness of the SOI layer can be easily prevented by preciselycontrolling the oxygen ion implantation, so as to form a thin film withuniform thickness.

Thus, this preferred embodiment enables the manufacture of an SOI waferthat has the SOI layer 32 with reduced film thickness nonuniformity. Thereduced thickness nonuniformity of the SOI layer enhances the currentdriving capability. In this way, the semiconductor wafer can be easilycleaved so that a section along MOS transistor channel direction isexposed, and a MOS transistor having a remarkably enhanced currentdriving capability can be formed on the semiconductor wafer.

While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

1. A semiconductor wafer manufacturing method comprising the steps of:(a) preparing first and second semiconductor wafers; (b) bonding a mainsurface of said second semiconductor wafer to a main surface of saidfirst semiconductor wafer; (b′) thinning said first semiconductor wafer;(c) implanting oxygen ions from said first semiconductor wafer side intoa neighborhood of a part where said first and second semiconductorwafers are bonded to each other; and (d) forming the portion implantedwith the oxygen ions into an oxide film layer by a thermal treatment. 2.The semiconductor wafer manufacturing method according to claim 1,wherein crystal directions of said first and second semiconductor wafersare shifted 45° or 135° with respect to each other.